BBD: parts inside

[Thomeeque]

 Hello,

BBDs and me again

I'm trying to emulate BBD line:



(of MN3207 for starters) in LTSpice and I even get some results already:


(click the pic for hi-res version, download source here: BBD_emu_LTC.asc)

but it's far from perfect - main issue is huge attenuation (growing with cell number, original MN3207 boosts signal!) and there's probably more.

But it's not surprise for me as I'm lacking basic knowledge about the parts inside the real MN3207:

• What type of FETs is used there (NMOS, JFET..)? What discrete type would be close?
• How should be S and D pins of FETs oriented?
• What is capacity of the caps?
• NEW: is there some exact way, how to state proper input DC bias?

Does somebody know?

Thanks, T.

[panterafanatic]

I believe the data sheet states P-chan or N-chan.

On my MN3207 data sheet, under the features it states, "N-channel silicon gate process." The clock is connected to ground/Vgg via the FETs, as well as the capacitors and inherent capacitance, so this is guesswork to me at least, but the datasheet sheet says that the clock input capacitance is a maximum of 700pF, divvied among 1000+ stages, that's less than 1pF per stage, which could just be the unavoidable inter-capacitance of the components in the IC.

[Thomeeque]

On my MN3207 data sheet, under the features it states, "N-channel silicon gate process."

On my too , unfortunately my knowledge about FET technology is so limited, that I don't know how to transform this statement to exact FET type - NMOS felt closest to me, that's why I used it, but I have no idea if it's correct. Plus which exact NMOS type I should pick, there's so many and variety of parameters is huge.

About S/D orientation it's similar, I have used what seemed more logical to me, but I have no idea if it's correct either.

The clock is connected to ground/Vgg via the FETs, as well as the capacitors and inherent capacitance, so this is guesswork to me at least, but the datasheet sheet says that the clock input capacitance is a maximum of 700pF, divvied among 1000+ stages, that's less than 1pF per stage, which could just be the unavoidable inter-capacitance of the components in the IC.

Hmm, output with use of 1pF instead of 100pF for C_bbd is not that different (it's just little more toothy), so maybe it's not that critical (and maybe 1pF is close to correct value).

Thanks, T.

[rustypinto]

See what documentation (patents, app notes, other write-ups) you can find from Panasonic and Reticon about BBDs. The MN30XX series used a higher-voltage (meaning up to 15V) PMOS process and the MN32XX used high-voltage (up to 10V) NMOS process. Reticon used a higher-voltage NMOS process for their stuff. Hopefully you can dig up the MOSFET gate feature size and find an equivalent device in your tool. Also, all of those capacitors that make up the "buckets" were either very small (~1pF probably) since caps take up quite a bit of die real-estate, or they used yet another MOSFET hooked up like a capacitor. The CD series of logic was high voltage, so i would probably start with finding an equivalent MOSFET used in those devices if you can't find out exactly what was used, especially since you can find documentation on those a lot easier (i know i could in my undergrad studies on device fabrication).

[nexekho]

It would be pretty interesting to see one of these made by hand in a box about the size of a MIDI keyboard :p

[edvard]

Holy crap!! For even just a modest 512-stage unit, it's going to be frickin huge and potentially expensive.
Unless you can find super-small surface-mount MOSFETS for a few cents apiece at the most.

Then again, I kinda dig insane ideas like this... 

[R.G.]

Be aware that the MOSFETs inside a chip may have dramatically different characteristics than discrete devices because they can be optimized for just one task, no matter how odd that would be in a discrete device.

I'd be interested in seeing how this might be with tubes. Something like 3000 12AX7s? 

[Mark Hammer]

I suspect that one of the most serious limitations of traditional BBDs is that the caps in them are kind of leaky.  As a result, the worst case scenario is to use a BBD at its longest delay-time with more than one iteration.  Exceeding the "safe" storage duration of a cap, and doing so repeatedly, leads to successive degradations/misrepresentations of the original signal.

Conceivably, a discrete version of a BBD could involve better choices of the storage caps involved such that one could hold the sample for a fairly long time without appreciable leakage/degradation.

[Thomeeque]

 Hello guys, it's pretty late here, I'm too exhausted (and boozed a little ) to answer anything smart at this moment, so just one note:

I do not plan to physically build it, I just want to emulate it to be able to easily study influence of thing like value of VGG, clock wave shape, overlap elimination etc. - just to simply see what happens when I change this or that - by few click of mouse (and without need of having expensive equipment)..

Cheers, T.

[Govmnt_Lacky]

Hello guys, it's pretty late here, I'm too exhausted (and boozed a little ) to answer anything smart at this moment, so just one note:

I do not plan to physically build it, I just want to emulate it to be able to easily study influence of thing like value of VGG, clock wave shape, overlap elimination etc. - just to simply see what happens when I change this or that - by few click of mouse (and without need of having expensive equipment)..

Cheers, T.

This sounds far too intelligent!

You are DEFINITELY NOT adequately boozed!!!   

[blueduck577]

A possible problem are the MOSFETs you are using.  On the real IC, I highly doubt the body of the FETs are tied to their source.  Try finding a 4-terminal MOSFET symbol and tying all the body terminals to ground.  And after you do that, the source and drain orientation shouldn't really matter.

[PRR]

Just FYI: the BBD is a "DRAM" logic memory device, a shift-register, with perhaps slightly different in/out systems. So the base technology is similar to Intel 1K DRAM from the early 1970s. MOSFET, but not CMOS, and probably not much like any device sold individually.

As blue says, the 3-pin/4-pin difference just may matter. And I have never been quite confident that the published circuit IS the correct topology; also the reality is that everything is too-tight (DRAM was very competitive) and interacts a lot.

Fix a 0V/+5V toggle and a pushbutton clock. Start feeding ones and zeros through. 512 steps later you get the same ones/zeros out. (Do this VERY fast: the _D_ in DRAM means the bits leak away in a small fraction of a second.)

The input bias is semi-easy. Feed a large signal. If biased high, the tops are clipped; too low, the bottoms are clipped. Find the middle where both are clipped. Reduce level to hardly-clipped. Re-bias, re-level, it's plenty good enough. (Number-lovers will next connect a THD meter and keep trimming/leveling until blue in the face.)

[nexekho]

Sorry to bump, but I had an idea, schematic'd it roughly in Falstad and it seems to work.  Three MOSFETs and a capacitor per bucket, but using a counter IC to syncronise the lot as a ring buffer instead of passing it down the chain.  I have no idea really but in theory this might have less signal degradation because it's not being passed around?  To vary the sample rate and thus delay time, change the clock rate into the 4017.  Each bucket is connected to three pins on the counter; (with overlap) the first unlocks that bucket's output path, then the second shorts out the capacitor to drain it, then the third opens up the input path to charge the capacitor with the signal.

Code Select Expand

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Yeah, that wiring's a mess.

[Galego]

That's just 6144 mosfets and 2048 caps for a 2048 stage bbd, how big would that be? 

[nexekho]

You'd also need sufficient decade counters and hardware to synchronise THOSE

[nexekho]

Improved design using flip-flops to control the sequence instead of a decade counter.  A few pennies more expensive but should make it easier to extend.  Also tidier.

The bit at the start with a JK+OR is just to insert a starting pulse into the chain to get it moving.  Is there a better way?  (injects pulses into the OR until the first flip flop responds)

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This is FUN!

[oldschoolanalog]

Reality check.
An MN3007 (1024 stage) BBD costs ~$3 US.
Hmmm...

[nexekho]

This sounds far too intelligent!

You are DEFINITELY NOT adequately boozed!!!   

[Thomeeque]

 Hey guys,

thanks for all your posts, sorry for not responding so long, blueduck577's "four-terminal NMOS with body grounded" hint moved me forward significantly* (thanks!!), but then I had to switch to something else again.

*At least now it looks like the value is travelling through the line losslessly (attenuation-wise; see s1024/s1025 signal), but there is still some problem at the very output:


(click the pic for hi-res version, download source here: BBD_NMOS4_emu_LTC.asc)

Unfortunately I don't have a time to play with it more now (and in the near future), but if you want to *please* go ahead, it really is fun

Btw. cool stuff, James!!

And just a small reminder:

I do not plan to physically build it, I just want to emulate it to be able to easily study influence of things like value of VGG, clock wave shape, overlap elimination etc. - just to simply see what happens when I change this or that - by few clicks of mouse (and without need of having expensive equipment)..

..because it seems to get lost really quickly

Cheers, T.

[PRR]

http://i.imgur.com/159Hn.gif