Foolin' With FETs

[FredB]

I've been simming the first few examples in the Foolin' With FETs article.  I had trouble getting the complementary push pull version working well.  So I decided to just sim the FET CCS by it's self.  I noticed that the FET CCS seem to work well only in a limited part of its full range.

I placed a voltage source between the CCS and ground.  Set the DC offset for 4.5v and then started exploring the performance of the CCS by applying an AC signal to the DC offset of the voltage source.

What I found is that the FET CCS only works well for say a 1Vpk AC signal.  Any greater AC signal Than that causes the current regulation to degrade rapidly.  This degradation goes from +/- just a few micro amperes to more than 100uA very quickly.

This lead me to try a BJT CCS with a 2N3906.  This seemed to work much better.  I calculated the ouput impedance of the FET CCS at about 290k, and that of the BJT CCS at about 1.5M.

Then I hooked up a 2N5484 with the BJT CCS and biased for Vcc/2.   The pair appears to produce a gain of about 450.  I noticed that the output wave form seemed to be clipping due to saturation.  So I raised the bias point a bit and now I get symmetrical clipping at about 78% of the maximum swing.

So what could I do with this I asked myself.  450x is a lot of gain for a pedal effect.  Well I thought,  how about linearizing the output with a NFB loop.  Easy peazy...  I set the gain for 10, and measured the distortion:   0.7% THD just before clipping.

Now I'm wondering if all that is really worth the effort when I could perhaps more easily just us an opamp.  What do you think?   

[arawn]

But sims can't tell you what the ear will actually hear or what will sound good in the real world. They are after all just simulations

[FredB]

Bread boarding is my next step.  I was wondering before I do if anyone here has had experience with FET CCSs.  From the sim it looks like the BJT versions will perform significantly better.

I have a couple goals in mind for this.  One high impedance buffers with low THD.  I have simmed darlington emitter followers that are able to achieve >500k input impedance, although the maximum swing is a bit less as is the THD than a simple JFET souce follower buffer.  So there appears to be a trade off there between better swing vs better THD.  That will have to wait for auditioning before a decision can be made.

Second I like to have gain stages without that common transistory harmonic distortion, high content of the first several harmonics due to non linearity.  In the right place that can add character, although it usually end up too much an over cooks the tone with harmonic content, making it sound, well, transistory.

[CynicalMan]

If you're going for low THD with high input impedance, go with op amps. Even a TL071 has a typical THD of 0.003% at a gain of 1, and an input impedance of 10^12 ohms (1T).

I don't think you'll find too many people here looking for low harmonic distortion.  

[FredB]

I don't think you'll find too many people here looking for low harmonic distortion.  

Yeah, I imagine so.  Although I am making a distinction between the clipping type of distortion and the distortion caused by non-linearity before clipping.  The latter type imparts a stale, 'transistory' character to the tone.  I would like less of that that to retain more fresher tone, then clip that as desired.

I thought of another question, has anyone tried using a pseudo-split supply typical for opamps with JFET buffers or BJT buffers for that matter.  I was just reading the Vishay AN-102 where they describe source follower circuits that use both a Vcc and a Vss, and was wondering how that might work out?  Whether it helped linearity or swing?

[CynicalMan]

I don't think you'll find too many people here looking for low harmonic distortion. 

Yeah, I imagine so.  Although I am making a distinction between the clipping type of distortion and the distortion caused by non-linearity before clipping.  The latter type imparts a stale, 'transistory' character to the tone.  I would like less of that that to retain more fresher tone, then clip that as desired.

My ears aren't magical enough to hear this. Have you ABX'd that "transistory" sound with the original sound?

Biasing a JFET buffer at 4.5V does increase headroom. They're often made like this:

[FredB]

Yep, that's about what I simmed, except I used a 2N5484 with a 10k source resistor and the total reistance for the bias divider of 2M with a 60/40 split.  Thiis gave 5v at the source and a total swing of about 4.25Vpk at about 2% THD.   I could go higher on the total bias resistance although what I used provided about 480k Zin which meat my goal.  

It was sharp of you to notice the bit about "magical ears."  I have yet to bread board any buffer circuits, might do that today.  2% would be a bit hard to hear.  Although I have bread boarded and ABed BJT gain stages and that's where I've heard the "transistory" harmonic content.  

Before clipping sets in that content can get higher then 10% THD.  Anybody should be able to hear that much distortion.  It warms the tone, some migh say in a tube like way, although at least to me it sounds distinctly transistory.  It's subjective.  I lack any other way to put it.

***

It just dawned on me that what I am looking for with the gain stages is something mid way between the open loop harmonic distortion of a transistor gain stage and the for all practical purposes zero harmonic distortion of a an op amp.  

So, I imagine this would have to be done with discretes and involving finding a workable hfe such that when the NFB is closed the harmonic distortion is reduce to say about 5% at full swing.  This would add warmth with out over cooking the tone with too much harmonic content.  I seem to have found a direction to explore.

Now that's sorted, the original question of the thread concerned JFET CCSs.  Have you tried anything with them?  Maybe I have something wrong in the sim:  


 


With the series voltage source set for 1Vpk AC signal on top of the 4.5V DC bias, the CCS is well behaved with dV/dI of 1/2.2uA which makes the output impedance of the CCS about 460K.

When the AC signal is raised to 2Vpk, the difference in the current goes to like +30uA/-100uA.  It seems to me that makes for a small range of good operation, too small.

[PRR]

> I had trouble getting the complementary push pull version working well.

"Had trouble" is not a useful problem description.

> FET CCS only works well for say a 1Vpk AC signal.

What is the DC bias point of the FET?

> BJT CCS with a 2N3906.  This seemed to work much better.

At what bias point?

And what are the drop-out voltages of JFETs and BJTs?

> With the series voltage source set for 1Vpk AC signal on top of the 4.5V DC bias, the CCS is well behaved with dV/dI of 1/2.2uA which makes the output impedance of the CCS about 460K.

> When the AC signal is raised to 2Vpk, the difference in the current goes to like +30uA/-100uA.  It seems to me that make for a small range of good operation, too small.

Your simulation may be over-complex. Why have 9V in the battery and 4.5V in the "AC" source? A 4.5V batt and simple no-DC AC source is the same thing. And clearly shows you only got 4.5V on the JFET. Peep the specs of your JFET, you probably find it has a knee at 2V to 5V. So it may do one thing at 4.5V, or 24V, but something else with 4.5V-2V= 2.5V across it.

BTW: that 1 Meg gate resistor is not needed. It is used to leak bias without shunting signal, but here you are not putting signal in the gate. And in fact the drain-gate capacitance is injecting drain voltage to the gate at high frequencies. And with the large gate-drain gain, Miller teaches that the cap is multiplied. "High frequency" could be starting below 1KHz.

K.I.S.S. The core test for a current limiter is to vary the voltage and plot the current. I aint got a P-FET but this will work nearly the same.



I swept 0V to 40V. Mostly flat, but knee at low voltages. If this is a 9V world, then I should look at say 0V-10V.

The V/I slope (resistance) 0V to 2.5V is 6.7K. This smells a lot like 6093(?) plus ~~600 ohms of bottomed FET channel. The slope 3V to 10V looks flat at this scale. Zoom and cursors show 700nA of variation over 7V of sweep, 10 Meg incremential resistance.

> 4.5V DC bias... the AC signal is raised to 2Vpk

What is the voltage available to the JFET+R when 4.5V is swung 2V peak? 2.5V. The double-arrow line shows that you are into the knee, starving the JFET so it acts like hole-soaked Silicon instead of a 3-terminal active device.

[FredB]

The series voltage source is to simply emulate an active device, either a JFET or BFT,  biased so that the drain/collector is at 4.5V.

I have seen JFETs without a gate in other schematics, I understand now without a signal the resistor is unnecessary.

I'm am unsure of the dropout voltages, I'll have to check into that.  This is my initial to do with CCSs and so I was copying from the article with the models I had just to get the idea.  I see the JFET was getting out of it's usualble range.  I do some sweeps with different parts to find that what will work.  I was looking to have the CCS biased for ~500uA.

***

I see, it only operates well above the knee.  So with the 2N5484 CCS biased for 500uA that allow a max swing of about 0.6 * 9V = ~5.6Vpp.  With a lower bias point I am presuming that swing would increase some what.

Well, that one mystery solved!

Now to have a look at the dropout voltage for the 2N3906 CCS...