JFET gain stage DESIGN

[clintrubber]

And JFETs do not ever quite "sound like triodes" because they have no plate-grid internal feedback (amplification factor is far higher than in-circuit gain).
Bah. If you want tubes, get tubes. They have never been cheaper (on the hamburger+gasoline price index).

I agree, going tube is often easier than go to great lengths to emulate them.

Yet there might be space constraints (or other requirements) & then it can be fun to try to come close - OR- make something, say a FET-based circuit, that sounds as 'nice' (...) as possible, while not necessarily emulating tubes.

I currently have an interest in/use for a circuit that doesn't use tubes, is compact and sounds 'better'/'more interesting' (...) than the opamp-stages it now uses. So want to see where substituting with FETs can bring that box.

Bye

[PRR]

> a quick compilation

Thanks.

Gm needs more info, as it will vary with current. Often the spec-sheet cites Gm at the *maximum* current (near Idss, so that column is a guide, though Idss spread is very wide). In much audio we run the FET at much lower current, thus much lower effective Gm.

NF Noise (hiss) Figure should also be checked. This varies widely with source impedance, also with frequency, and operating current. "0.5dB typ" may be measured at insane source impedance and huge current. Few FETs will hiss bad in reasonable guitar-system applications.

I'd say Cin is a non-issue in face of 300pFd of guitar cable capacitance and frequent use of 470pFd input shunts to reduce radio reception in bad areas. In a gain-stage, drain-gate C times stage gain gives Miller Effect much higher than the touted Cin.

[clintrubber]

> a quick compilation

Thanks.

Gm

NF

Cin

Hi Paul,

Yep, realizing that a quick comparison is just that, it sure needs a pile of conditions added to make comparing FET-types meaningful & accurate. 

Gm, Cin, NF: I had only time for pulling quick figures from the tables; for a more accurate comparison we sure need to look at the graphs & compare at identical (& like you say also at the more relevant) conditions.

Meant as a first rough-very-rough comparison when various JFET-types started to pop up in this thread.
The Harvard-circuit Gus mentioned uses the J231, for this thread he switched to the more common J201.

Likely a moot point, but as a brain-exercise for myself I'm interested in what the most suited FET would be for my intended supply rails (+/-12V).
The Harvard runs the J231 at +/-15V (if those zeners are indeed 15V) and Gus 'translated' to the J201 at +/-9V rails. I was triggered by a remark from Gus about FET-type related to rails, in another thread.


Cin: fully agree with the (non-)relevance of this for the first FET. Dunno yet how it would be for subsequent stages, but there its relevance might at least be secondary as well (those cheapskate or cramped-for-space types (guilty) prefer to emulate tube-preamps by replacing all triodes, so there'll be a few additional FET-stages.
See for instance also the Fender Harvard (early solid state, not the II) schematic that Gus has mentioned.

http://elektrotanya.com/fender_harvard_018023.pdf/download.html

NF: like you say, less relevant. Say comparable to Cin-reasoning: if, then only important for first stage, unless after severe tonestack-attenuation, then there a reasonable quiet FET desired as well.

Bye

[Gus]

39K was picked for two reasons, one Id less than IDSS at 4.5VDC across the 39k and can anyone guess the 2nd?

Look for the solid state fender Harvard amp schematic.

Let's add for completeness of this nice thread:

I assume for mimicing the same source-impedance (as presented to the next stage) as the 'original tube-version' has:

100k plate resistor, in || with the ECC83 internal R of 62k5  --> 39k

Bye

Yes to sim the rp for a stock tone stack.

[clintrubber]

Yes to sim the rp for a stock tone stack.

Thanks

[clintrubber]

BTW/FWIW*, w.r.t. J201, from Teemu Kyttälä, Solid-State Guitar Amplifiers (online pdf), pg208:

"Note: One should avoid using JFETs with low IDS – especially in buffering circuits.
For example, J201 is a commonly used FET - probably because it was once used in
the famous "Till" guitar preamplifier and "FET Preamp Cable", both designed by
Donald Tillman. However, the gate cutoff voltage VGS (OFF) of a J201 is about the
lowest amongst all depletion mode JFETs and with moderate source resistor values
this device can't even handle input signals that are greater than few hundred
millivolts peak-to-peak. This FET is a horrible choice for buffers and basically for
common source circuits as well: In an equal circuit, a higher current FET, like J309,
can handle input voltages higher than 1 VPP and even offer slightly greater gain.
Although popular, J201 is really not that marvelous device. Note that Donald Tillman
originally substituted a higher current model with a J201 solely because of improved
noise performance. Let this be a lesson to you: Always base your component selection
principles on circuit theory – not to a fact that a particular component was used in
some famous circuit! It might have worked there – likely it will not work as well in
another application."


*: less relevant w.r.t. the original topic of this thread (added rail, larger rail-distance)

[PRR]

> Always base your component selection principles on circuit theory

And understand that theory.

I see what Teemuk is saying and it is quite correct as far as it goes.

But then how can we ever use a BPJ transistor? What Vgs(off) really is, is the distance from full-on to full-off. In a BPJ this is typically 60mV! (Take 10V and 10K, bias the base voltage so that collector is almost zero. Now reduce base bias voltage by 60mV. Current goes down by 10X, collector will come up to 9V out of 10V.)

Another nitpick: Teemuk's correlation of "high current" and "high Vgs(off)" IS true for FETs of the same geometry, it is not true for FETs of different geometry. Consider ten matched J201s in parallel: the total Idss is 10X higher, but the Vgs(off) stays the same (neglecting the practical specification-point that Vgs(off) is typically measured not at dead-zero but at perhaps 10nA, which is 1nA each in our 10X array, which will need a wee bit more Vgs to go "off"). Current is largely about area, Vgs(off) is largely about depth of processing.

[PRR]

> what the most suited FET would be for my intended supply.....

Not 9V.

We ground the gate. The source has to be part-of Vgs(off) above gate/ground. The drain has to be most-of Vgs(off) above the source. Vgs(off) can be found from 0.2V to 8V, and you can't buy a narrow selection (maybe SmallBear, if you pay his staff). Taking part-of Vgs(off) as sometimes 3V, Drain has to be over 6V *minimum*, which is most of the 9V supply gone. Then we probably need to idle at 7.5V, the middle between 6V min and 9V max. That leaves little for output. Also quite a low value for source resistor. While we 9V folk lean to Vgs(off) far less than 8V, we sometimes have to take what we get.

> +/-12V ...  +/-15V

Between 24V and 30V, there's no great difference. Both are so much more than the hardly-ample 9V that either can work fine.

To over-simplify: Fender biased two of those stages with Gate "at" ground, allowing a huge 15V in source stabilization resistance. IIRC, 330K. Drain loaded in 150K. Source and drain currents are equal. If drop is 15V in 330K, it will be 7.5V in 150K. Drain is *sure* to be very-very near half of the zero to +15V range. Actually Fender biased a little lower, but the net result is most of 15V swing peak-peak, 5V RMS out.

Another point: JFET voltage gain goes up when designed for higher supply voltage, and goes down as about the square-root of current. Practical limit is the 30V-40V G-D breakdown voltage. However you could run +/-30V with gate near ground and most of the -30V only appearing in a source stabilization resistor.

Now that you have very exact control of current you can aim-down from 1mA to 100ua or 10uA, get 3X or 10X the voltage gain. The limit comes when you can not drive the load. If you steal tube-amp values, 200K is an upper limit (while you can use 1Meg resistors, stray capacitance tends toward 200K at the top of the audio band, unless you hammer at it).

The drain resistor should be 2X (to 5X) times lower than 200K, say 100K or 40K. Dart at the resistor rack selects 47K. With +30V supply and op-point around +15V D-S (and 15V across 47K), current should be 0.3mA. J201 Gm at 0.3mA is (how interesting!) 1.5mMho (1,500uMho, a familiar number). 1/Gm is 667 Ohms. gOs at 0.3mA is around 5uMho, or 'plate resistance' is 200K. Taking 47K 200K and 200K, 32K total, voltage gain is 48(!!). Taking maximum output as 30V/2.828= 10Vrms, gain of 48, maximum input is 0.2Vrms (stupid low-volt devices!). But we can raise that 0.2V to 0.5V by making effective 1/Gm 2.5X higher, which means adding 1.66K in series with the source's AC path (1.7K in parallel with an assumed 100K from source to -30V). Voltage gain is 19, 10Vrms out implies 0.5Vrms max input, which covers most guitar and hotter axes can use hi/lo jack input.

Note that in Fender's plan, V+ and V- do different things. The plus sets the maximum output, which maybe wants to be large. As noted, this could be +30V without harm. The minus is *only* to over-whelm the un-certainty of Vgs(off). For J201 we have spread of 0.3V-1.5V, a 1.2V uncertainty. -12V would reduce variation to 10% (+/-5%) which is plenty good for an audio amp (we mostly want to stay away from both rails, not hit an exact op-point). Even +35V/-10V would be a fine design. However doubling the voltage may quadruple the power demand, while not even giving twice the headroom, so may be diminishing returns. And the ways of getting both-ways supplies often favor about the same on both sides. So rounding-off from +40V/-10V to +/-15V or +/-12V sacrifices little and may be more practical.
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[Gus]

An older thread http://www.diystompboxes.com/smfforum/index.php?topic=103492.20
I used 201s because people seem to build with them.  I would use a different jfet in a build.  Based on textbook app note circuits
Look for the difference from the first post and gritz's posts at the end