Multiple PT2399 in series for mega long delays - what have folks done?

[R.G.]

One man's ceiling is another man's floor. 

[deadastronaut]

just a thought: a bit OT but it might be able to be applied circuit wise to get long delays...

years ago i remember linking up 3 delay pedals and summing the delays to get a really long delay..this is what i did IIRC...
(it was a long time ago i asked my mate to remind me of how i did it)...so bear with me ok..

buy or make a 2 mono into 1 stereo in adapter, plug into delay 'in' the one nearest guitar, chain desired amount of delays after 1st pedal, turn all mix/balance to 'wet' only. plug lead from guitar into mono 1 socket on adapter... plug separate lead into mono 2 socket as a pure 'out' and feed to desk <from the adapter>.... take output lead plug into last output in chain and feed to desk as delayed out...

i think that was it...maybe this could be applied circuit wise into what your after...it'd be cool, and maybe less dirty...just my 2p..

[earthtonesaudio]

0-2.5VDC into pin 6 will result in approximately minimum to maximum delay times.  Since each pin 6 can source maybe 1mA at the lowest CV in, the voltage source needs to be able to manage that.  A bipolar supply for the op-amp would be ideal, but by no means is that the only approach that would work.

Of course that would do nothing to address the clock synchronization or potential for heterodyning.  My gut tells me that once you get to that level of detail it would be cheaper/easier/better to move on to a FV-1 or similar alternative.

[frequencycentral]

Ok you've talked me into it. No, wait.........!

[frequencycentral]

No, wait.........!

[Fender3D]

Hey Rick that's 10m 45s delay !!!! 

And no fuzzy letter... 

[cpm]

I think I must have exercised every possible scheme for ganging up PT2399s, including a few that haven't been suggested. The conclusion I came to is that if you want PT2399s in series, you have the obvious issues: quantization noise at delays over about 400mS, heterodyning and quantizing+heterodyning noise in series, loss of treble if you filter to get rid of the noise with a high pass cutoff. Princeton Technologies was not interested in changing the innards or even telling me more about the insides for less than a 100K unit order.

I did solve the heterodyning issue by locking the oscillators up. That still left quantization noise and its other artifacts for longer delays. I did get a 2 second delay working, but in my judgement, the necessary standard of audio quality was not practically reachable.

My conclusion is that the PT2399 is usable up to 400ms, full stop. Beyond that, you're accepting steadily declining audio quality.

Agreed

the stopper for chaining PTs is quantization noise. You have to filter in between stages to avoid it getting worse at the end. So even tuning the stages at small delay times at the end the sound has lost quite a bit of its brightness, and background noise will add up with each stage.
The compromise i think is 2 PTs. To me it sounds better 2 ics at 150ms each, than 3 at 100ms.

Beyond that sensible limit, i have tried:
companding: it helps but still there is noise, and the compander has its own noise figures and artifacts
dynamic filtering: a switched capacitor filter slaved to the PT clock, to keep short delays clear, and longest times more severely filtered
pre/de emphasis: some threads around here suggest that this is even worse due to the delta modulation adc

And on the interface side:
clock is internally generated from a vco, controlled by a current source. Current mirror is the ideal way to synchronise them, but there are actual tolerances or variations that wont make then perfectly matched, thus generating heterodyning noises. At 3 PT count there is a nice "woshh" ringing on the grounds...
The oscillator looks very sensitive to the current tha runs through the chip. A small variation in current will make a drift and slight chorus effect, even at steady settings the passing of audio seems like it makes slight variations on pitch...
Vco current-to-time is a logarithmic relation, so implementing a precision controller in not specially easy, taking into account the log scales, deviations, temperature compensation... It could be done with a uC using feedback from the PT clock, but still there will be variations across chained chips...

i am at the point of balancing all of these methods, even doing a feasible tap-tempo controller, but everything seems like a too-much, too-big, too much time, for something that will still suffer from a non satisfactory end result anyway, just like RG said

[earthtonesaudio]

Seems like there is the potential to tap off the digital (delayed) output by omitting the caps typically connected to pins 7 and 11-12, and taking the output from pin 12.

Then you could add a second IC in series and use pin 16 as a digital input by omitting the capacitor typically connected between pins 15-16.
As long as the clocks were in the same neighborhood I think you would not lose very many bits of data.  From reading between the lines of the datasheet I think the clock is about 16x faster than the data rate.

I need to get some more PT2399s to see if this works, at the moment I only have one available for breadboarding.

[cpm]

Seems like there is the potential to tap off the digital (delayed) output by omitting the caps typically connected to pins 7 and 11-12, and taking the output from pin 12.

Then you could add a second IC in series and use pin 16 as a digital input by omitting the capacitor typically connected between pins 15-16.
As long as the clocks were in the same neighborhood I think you would not lose very many bits of data.  From reading between the lines of the datasheet I think the clock is about 16x faster than the data rate.

I need to get some more PT2399s to see if this works, at the moment I only have one available for breadboarding.

yes, the oversampling looks like 16...

so you are saying, bridge the raw data from one PT to another... like a memory extension...  interesting indeed, i have them on the breadboard, will try it...

[earthtonesaudio]

Cool!  Let us know how it turns out if you could. 

[Deneteus]

I had the same idea this week and found this thread. I would like to try that in Stereo. If noise is the issue can't the sound coming out be recorded on to another cheapy sound chip and then passed off to the next delay chip. For example a bridge between the chips. It would be kind of like a digital tape echo right?

[cpm]

Cool!  Let us know how it turns out if you could. 

nothing clear... only noises!!

by the way... went into a precission current mirror trying to match 2 PTs VCOs, and actually it got worse, the heterodyning noise is more severe that way.
The best approach seems to be mismatching the delay time in a proportion that wont make wind noises from the clocks fighting in.

[R.G.]

by the way... went into a precission current mirror trying to match 2 PTs VCOs, and actually it got worse, the heterodyning noise is more severe that way.
The best approach seems to be mismatching the delay time in a proportion that wont make wind noises from the clocks fighting in.

Yep. That's what I found. You either have to lock them up solid or make them very mismatched. Very mismatched makes the clock noise hide under the inevitable quantization noise, and near-locked brings up heterodyne squeals that are very obvious.

There are two ways I know of to lock up the oscillators. Here's the one I'm at liberty to talk about: make the PT2399 clock into the VCO of a PLL.

The PT2399 has a clock out, but no clock in other than the current input for delay. The VCO input pin cannot be successfully driven with an external clock signal for clock sync. But if you add a phase detector, charge pump and low pass filter, you can make it into part of a VCO. If you feed this an external clock (and get the PLL design right), then the digital clock will follow the input frequency in lockstep. There is still phase jitter, but this turns out to be random and the audio effect is inaudible under the quantization noise. It works.

At a cost. The PLL components are most easily and economically done with a packaged CMOS PLL chip, using only the phase detector and charge pump. To this you have to add a filter, which is easy, and a driver for the VCO pin input, which is harder to get right. This added circuitry runs at the clock frequency of the PT2399, which is up in the megahertz range, and digital, so layout suddenly gets critical. The cost in terms of additional circuitry and required layout space and discipline is considerably higher than adding another PT2399.

In the end, I wound up deciding that for my purposes, it was impractical. Most players think they need delays of a second or more, but 99.9% of the time do not USE delays that long.

The other grail quest of delays is tap tempo. Yes, the PLL approach can make a real tap tempo out of a PT2399 - at another cost. It takes a clot of circuitry to convert tap intervals into the desired clock frequency. Once you have the desired clock frequency, the PT2399 will follow. This is most practically and economically done with a microcontroller, which adds another fast digital chip to the basket.

When I got through all that, I decided that the PT2399 is good for what it does - delays up to about 400mS, which covers the vast majority of what guitarists really use. It can do more - if you're willing to pay the considerable freight to get there. 

[cpm]

There are two ways I know of to lock up the oscillators. Here's the one I'm at liberty to talk about: make the PT2399 clock into the VCO of a PLL.

The PT2399 has a clock out, but no clock in other than the current input for delay. The VCO input pin cannot be successfully driven with an external clock signal for clock sync. But if you add a phase detector, charge pump and low pass filter, you can make it into part of a VCO. If you feed this an external clock (and get the PLL design right), then the digital clock will follow the input frequency in lockstep. There is still phase jitter, but this turns out to be random and the audio effect is inaudible under the quantization noise. It works.

you mean use PT1 clock as reference, and make the PLL control PT2 VCO based on the phase difference between both clock outputs... right, overly complicated
For locking in a proportionally different frequency i just use a current mirror slightly unbalanced, that is 2 o 3 npn transistors and a samall resistor

The other grail quest of delays is tap tempo. Yes, the PLL approach can make a real tap tempo out of a PT2399 - at another cost. It takes a clot of circuitry to convert tap intervals into the desired clock frequency. Once you have the desired clock frequency, the PT2399 will follow. This is most practically and economically done with a microcontroller, which adds another fast digital chip to the basket.

i currently use a PIC to divide the PT clock to drive a swithed filter, no problems there, and i guess it could be extended to control the current on the VCO pin using the clock output as feedback. Another matter is laike you said, if it's really worth the effort

[R.G.]

Another matter is laike you said, if it's really worth the effort

Yep. I learned a long time ago that you can usually do anything once if you have enough time and money. Doing it over and over in a reasonable time for a reasonable amount of money can be tough or impossible as a practical matter.

[earthtonesaudio]

It simplifies things somewhat to realize that the VCO is in fact voltage-controllable.  See here.

[R.G.]

It's actually current controlled. They make that "voltage controlled" with the internal resistance. A transistor current mirror at ground works fine.

[earthtonesaudio]

Connecting a voltage source directly to pin 6 works.  You just have to mind the details, like the fact that the voltage must be between 0 and 2.5V and be able to provide at least a couple mA.  If you had a bipolar supply handy for the op-amp, it would be the obvious choice.  With a single supply, building a discrete op-amp vs. a current mirror is a wash... Until you want to do other "op-amp" operations, then the discrete op-amp wins out, in my opinion.

[R.G.]

If it works for you, use it.

That is practically the mantra of the engineer. It illustrates one of the big differences between engineers and scientists. Both of them want to know how things work. But engineers have deadlines, all the time. It has to work by the deadline. If that requires using elaborate tables of how it worked before, approximations and guesses, so be it.

Engineers *will* use what works, even if they can't get a closed-form solution. 

[merlinb]

Connecting a voltage source directly to pin 6 works.  You just have to mind the details, like the fact that the voltage must be between 0 and 2.5V and be able to provide at least a couple mA. 

It doesn't have to vary between 0-2.5V; it depends on the resistance you put between the two. If you use 200 ohms then it only has to vary between about 2V and 2.5V, for example.