IC in parallel

[Dimitree]

hi guys
I need to put many ICs in parallel, i.e. pin 2 of IC1 connected with pin 2 of IC2, pin 3 with pin 3, and so on. this is for a little project that uses DRAM chips.
I'm having trouble trying to design a proper pcb, it would take so much space and it double side is a MUST.
I was thinking about stacking the ICs and isolating the 2 pins of every IC that have not to be in parallel with others. Is that a good solution?
another idea I had was to use 2 pcbs in parallel, forming a sort of ladder, with the 2 pcb that twist the ICs, but that would require to fold the IC pins
like this (or with the ICs in vertical, not horizontal) (sorry for the pic :-D)
http://imageshack.us/photo/my-images/819/immaginego.gif/

[alparent]

I would stack them up and just bend straight pins you need isolated.

http://eda360insider.files.wordpress.com/2011/11/128kbit-stacked-dram.jpg

Would be a pain to replace any dead chips after that .....but what are the chance of that happening?

[Dimitree]

the problem is that I will use DRAM chips, and doing that would mean that I need to solder directly the pins. is that doable for hobbyst or DRAM are more fragile than usual ICs?

[caress]

perhaps have them offset slightly and solder the ICs to either side of the PCB?  that way you can physically have the pins very close to each other while maximizing board space.

[alparent]

isn't that dram in the picture I posted?

[amptramp]

There used to be a form of construction called cordwood where there were two circuit boards and components were strung between them.  This was from the 1950's to 1960's - I have seen some of it and would make sense for your design, although repair would be almost as much of a nightmare as stacked IC's.  The pins on one side go to one board and the pins on the other go to the other board.  All of the pins which are paralleled would be connected together and the pins that had to be separate could go off the end of the board so that it would not interfere with the paralleled pins.  It would allow you to select the spacing between devices for adequate cooling or for metal plate heatsinks between devices.  All IC leads would be bent out flat to do this.

[Dimitree]

thanks for the tips guys!
corwood is exactly what I was thinking about
I could use that with SIL socket so repair wouldn't be that hard

[pinkjimiphoton]

yah, the easiest way is to just stack 'em on top of each other, so the pins all touch and then just kiss 'em with a little solder. if you're on them fast you should be ok. i've had some good luck doing that with dual opamps, and even the pt2399.

[iccaros]

why would you do this with DRAM??? how do you address the chips? as you must give an address to seek infromation? or are you not putting address lines in parallel?

[Dimitree]

exactly, DRAM chips are in parallel, so they share the same address.

[iccaros]

exactly, DRAM chips are in parallel, so they share the same address.

DRAM is very noise and static sensitive. Doing Parallel buses is ok, but has to be designed well, but you need separate  address lines in order to get data out, or else all DRAM modules would store the same data in the same place, you did not gain memory or speed and added a lot of noise.  DRAM does use a parallel bus, meaning that there are 9 individual wires and the controller put a 1 or zero in all of the lines at once, not that all chips wire together for the address and dateline. The datelines are also parallel.
so out of  a pic you would have 9 pins (or an I2C to parallel adapter or a DRAM controller)

Pin 1    0v
Pin 2    1V
Pin 3    0v
Pin 4    0v
Pin 5    0v
Pin 6    0v
Pin 7    0v
Pin 8    0v
this would give you an address
but if you connect multiple chips to the same parallel bus you would address all of the chips the same, putting the same data in all of the memory chips at the same time in the same place.. no gain.

so each DRAM module needs its own parallel bus to address and to add memory it is recommended to use a DRAM controller. At work we use FPGA's to both create DRAM controllers for our AUV's. But we are transferring large data sets.

[Dimitree]

thanks for the explaination,
I'm not that expert, so please correct me if wrong, but, if I address all of che chips with the same addres, yes I will use the same place for each chip, but not the same data since every chip will store in that place the bit that it got on its individual input, right?
so at every instant, all the chips will store their own value, so if you use 8 chips, you'll have a byte composed by 8 bit coming out from the 8 chips at the same position.
It's not like this?

[iccaros]

There are many issues with putting DRAM in parallel, I will send them out latter, I do not have much time, but did not want to have you think I was just being an A$$, that just comes out.. its the engineering background. IF you could supply which DRAM chips you were thinking and a purpose I could give better advice than just no do it, but in general separating out the datalines  could work but at 1024 clock cycles @ 16ms duty cycles for each operation, you better be prepared to handle a lot of data even if its blank.. Plus reading a blank memory bank returns an error unless you are testing. you have a CAS and RAS update which get tricky, this why each dram chip  in our configurations have their own controller.

If you are coming from a Microprocessor you have issues there, what are you trying to store? and can EEPROM work better?  as its much less complex, but dealing with one chip can be hard, adding more is more noise, more loading of a week signal and  just a lot of issues which I will explain better with more time tonight.

[Dimitree]

thanks for the help
actually I'm just experimenting with logics and digital chips to have some fun so no precise purposes..and in the meanwhile I'm studing informatics so I think this fun could be usefull to learn something about low level hardware
I saw some digital delay schematics that were using those DRAM in that way, for example EH 16 second delay. Obviously today it would be way easier to use other kind of memory or a micro or DSP, but I've already did that so I want to try the basics
I guess it's not a problem for a delay application (built like: ADC --> DRAM --> DAC) to read and handle tons of data, blank data most of time, since we don't store data for undefined time but we just need to hold it for some time before send out to DAC
btw it works in those applications so I guess it could work if I try to do something similar..

[DavenPaget]

thanks for the help
actually I'm just experimenting with logics and digital chips to have some fun so no precise purposes..and in the meanwhile I'm studing informatics so I think this fun could be usefull to learn something about low level hardware
I saw some digital delay schematics that were using those DRAM in that way, for example EH 16 second delay. Obviously today it would be way easier to use other kind of memory or a micro or DSP, but I've already did that so I want to try the basics
I guess it's not a problem for a delay application (built like: ADC --> DRAM --> DAC) to read and handle tons of data, blank data most of time, since we don't store data for undefined time but we just need to hold it for some time before send out to DAC
btw it works in those applications so I guess it could work if I try to do something similar..

The last time i rummaged through my DSP amp , it had a SRAM and DRAM all together 

[iccaros]

thanks for the help
actually I'm just experimenting with logics and digital chips to have some fun so no precise purposes..and in the meanwhile I'm studing informatics so I think this fun could be usefull to learn something about low level hardware
I saw some digital delay schematics that were using those DRAM in that way, for example EH 16 second delay. Obviously today it would be way easier to use other kind of memory or a micro or DSP, but I've already did that so I want to try the basics
I guess it's not a problem for a delay application (built like: ADC --> DRAM --> DAC) to read and handle tons of data, blank data most of time, since we don't store data for undefined time but we just need to hold it for some time before send out to DAC
btw it works in those applications so I guess it could work if I try to do something similar..

If this is it http://stecrecords.com/gear/eh16/EH16Sec2.GIF, This is interesting, First the Data in and out are not parallel as there is only but only one of each per chip, and they are multiplexed by the RW pin in a sense. These are ran to their outputs. The address lines are ran in parallel, and a timing circuit steps though all of the cells one at a time on all chips at the same time. Since these are 1bit memory chips this gives the same effect as having a 64K*12 or in other words you have 12bits of resolution. Since this is a representation of audio we do not care about errors which you would have a lot of, and even a case, before a CAS and RAS cycle, of memory possibly being out of step.  This goes to a Digital to Analog converter which looks to also receive clean analog signal for mixing, but this is hard for me to read that part I see, the audio comes in through a Analog to Digital converter (see the box with the two triangles and trance the lines to the DI) , and rides the Data in lines and the RW bit is set. At play back the individual bits are sent back the same line, and since the digital to analog converter is the side with an input, it decodes the audio. If you have the delay off, or on, the original audio is passed from the AD to the DA.  


This is kind of cool in that its not using the ram as memory as we think in computers but more in line with tape.. where it has no ideal where anything is stored and its not retrieving,, the address rotate through no matter what, in a cycle, most likely set to the time of the delay. And if the RW bit is set it records, if not its playing..
Also no matter what the audio going thought the pedal is converted from analog to digital and back, even on bypass (so it looks). When delay is on, the non affected signal is still converted to a 12bit parallel word and translated back. Which means all audio is degrated to 12bit resolution. Most would not know this is happening and can not hear it, but I can see where you may loose some dynamics.

Thanks for Sharing.. Now I know why you would want to parallel DRAM, but it must be specific type and use..

This is much more rudimentary DRAM than I had in mind. Tthey are not gaining memory for say, but gaining bit resolution

[Dimitree]

thanks for the explaination
I have another example of this DRAM application that uses a different chip (4864) and this chip have different pin for input and output, so the ADC output is not directly connected with the DAC, so only the delayed data goes out to the DAC. The rest is pretty much the same.
what if we put another DRAM chip instead of those used there? I mean, those chips are 64k, if we put 256k or more (assume they have the same pinout and specs) we don't gain anything since the "address controller" is built to address 64k, so the rest will be blank and never accessed, right?

[iccaros]

I mean, those chips are 64k, if we put 256k or more (assume they have the same pinout and specs) we don't gain anything since the "address controller" is built to address 64k, so the rest will be blank and never accessed, right?

yes, but you can adjust that changing the  address CKT, I would use a PIC or AMTEL micro-controller, you get more control could replace some of the other functions, and it will give you more record time,  but grab the datasheet. you need a ADC and DAC that matches the total bit resolution.
If you had two 256K*8 you would use 2 to get 16 bit resolution. They used 12 to get the 12 bits..
for this case speed is not a true factor so you can use some older chips.

But I am thinking 1bit chips would act more analog as there is so small a delay, as you add bit, you get more delay in response, this is why they keep upping clock cycle. what Chip do you plan to use?

[Dimitree]

If you had two 256K*8 you would use 2 to get 16 bit resolution. They used 12 to get the 12 bits..
for this case speed is not a true factor so you can use some older chips.

But I am thinking 1bit chips would act more analog as there is so small a delay, as you add bit, you get more delay in response, this is why they keep upping clock cycle. what Chip do you plan to use?

Unfortunately I haven't found any DRAM chip with multiple bit that have Input and Output pin divided. Only 1bit chips have that, so I guess I can't do nothing more than using 4864 if I want to keep this principle (and this is the main aim)
if I'd use 4164 instead (or 41464 --> 4x 1bit in a single package) I would have IN and OUT physically connected with ADC + DAC so I would have the whole signal converted and not only the delay.

[iccaros]

you can have the input and output as the same, you just can not record and play back at the same time.. with the 4 parallel bits, you can use 4 of those to make 16bit or 6 to get 24bit resolution, but this is easy to experiment with bread board and see what you like, it may be too slow for these short times, and cause distortion, if you can hear that distortion is whole other argument. 

I would not stack the chips more than two as you add capacitance between solder and the gap each pin will have, its like stacking glass, if you have 10 individual sheets of glass stacked, no light can penetrate as you loose 10% if light between the surfaces of glass. While if you just make a 10foot block you can see clearly as you have only two surfaces. if you stack two chips and run that parallel to two chips and so on you will have better contact, individual chips ran over a ground plane (PCB?)  would be best for noise and error.   

I would have IN and OUT physically connected with ADC + DAC so I would have the whole signal converted and not only the delay.[\quote]
That is what EH did in theirs..  the out of the ADC runs to the in of the DAC with the Multiplexed I/O coming from between them.