Clocking MN3007s at high clock rates - questions

Started by MR COFFEE, February 26, 2012, 05:43:53 PM

Previous topic - Next topic

MR COFFEE

Hi all,
Well, I've got a new project on the drawing board - an updated version of the CLS-222 using currently available chips like the MN3007. The MN3007 has a bucket line twice as long as the TDA1022, and since 3 of the 4 delay lines in this beast are clocked at pretty normal rates, I figure I can just double the oscillator frequency that drives the BBD clock rate and switch the bias to suit the MN series.

Here's the questions:

1) The CLS-222 uses one CD4013 dual FF to clock each BBD, and just leaves one of the FFs in each IC unused, presumably to limit dissipation.

       Any opinions on whether to parallel the second FF in the CD4013 since it will be driving the BBD at double the clock rate (around 100 Khz) for the delay lines that are run at 100 Khz or thereabouts, or whether I need to use a CD4050 buffer for each clock line (there are 6 in an IC, I would think 3 in parallel per clock line?), or other suggestions...

2) For the one BBD that the CLS-222 clocks really fast (up to 150 Khz, which times 2 for clocking the MN3007 is 300 Khz), does the CD4050 buffer sound like a good plan?


3) Or should I spring for using the CD4050 buffering for all the clock lines?  Anybody know how warm these ICs get driving 700 pf x2 (for both clock lines) at 100 Khz?

4) And will the CD4013s get too warm directly driving the clock lines at 100 Khz?

Seems like Mark Hammer had done some work with MN3007s at high clock rates at one time... Mark, have you got any experience you'd be willing to share?

Or someone else who understands the dynamic dissipation of CMOS driving really heavy capacitative loads at high rates? I'm more of a "thumb test" kind of guy. :icon_lol:

Thanks,

mr coffee
Bart

Mark Hammer

I actually have very little experience in the area.  I just collect others' experience. :icon_wink:

Take a look at the John Hollis Ultra-Flange for an idea about what to do.  It uses an MN3007, and sticks a trio of 4049 invertor sections in parallel to drive each of the clock lines with more current..

Fender3D

#2
Quote from: MR COFFEE on February 26, 2012, 05:43:53 PM

1) The CLS-222 uses one CD4013 dual FF to clock each BBD, and just leaves one of the FFs in each IC unused, presumably to limit dissipation.

      Any opinions on whether to parallel the second FF in the CD4013 since it will be driving the BBD at double the clock rate (around 100 Khz) for the delay lines that are run at 100 Khz or thereabouts, or whether I need to use a CD4050 buffer for each clock line (there are 6 in an IC, I would think 3 in parallel per clock line?), or other suggestions...


You will use one 4013 per BBD to avoid etherodyne issues

Quote from: MR COFFEE on February 26, 2012, 05:43:53 PM

2) For the one BBD that the CLS-222 clocks really fast (up to 150 Khz, which times 2 for clocking the MN3007 is 300 Khz), does the CD4050 buffer sound like a good plan?


In my MXR 117 clone 4013+3007 reach ~1MHz with no buffers (as long as you keep the tracks from 4013 to 3007 reasonably short and not too near GND tracks)

Quote from: MR COFFEE on February 26, 2012, 05:43:53 PM

3) Or should I spring for using the CD4050 buffering for all the clock lines?  Anybody know how warm these ICs get driving 700 pf x2 (for both clock lines) at 100 Khz?


4013 won't get warm 'cause capacity, just the squared waveform will get rounded 'cause the higher the capacity the lower the bandwidth (therefore it may have issues with BBDs)

Quote from: MR COFFEE on February 26, 2012, 05:43:53 PM

4) And will the CD4013s get too warm directly driving the clock lines at 100 Khz?


See point 2
"NOT FLAMMABLE" is not a challenge

oldschoolanalog

300 kHz is a very pedestrian clock rate for a 1024 stage BBD. There are no special considerations necessary really. Just use good common sense and lay it out carefully. :icon_cool:
Sounds like an interesting project. Could you please post a schematic?
Thanks and Happy Soldering!
Mystery lounge. No tables, chairs or waiters here. In fact, we're all quite alone.

12Bass

Can't recall the source right now, but from what I've gathered if a buffer like a 4049 is going to be used, it is better to use only two buffers in parallel (e.g. A/DA redesign), as three compromises the quality of the clock signal.  As others have mentioned, the lowish clock speeds discussed above may not benefit from buffering the clock signal.  With clock buffering, the SAD1024A happily screams up into the stratosphere.... 
It is far better to grasp the universe as it really is than to persist in delusion, however satisfying and reassuring. - Carl Sagan