PWM phasers - has anyone scoped the output? (calling PWM phaser experts!!)

[Gurner]

So I'm dabbling with a one stage PWM phaser (just to bed the concept away!), there's scant info about PWM phasers them on the net....there are a couple of schematics, but it's not clear to me what's going on.

For example, consider this one....



it's basically showing a switch...I'm figuring here that the phase shift concept is that the phase shift is going to be related to the ratio of the switch being open/closed for....but what type of clock signal is applied to the switch control gate? Is it a ramping/deramping duty cycle from 0 to 100% & back down again? (also what frequency ios the clock typically?)

I thought I'd replicate the above but with a mosfet in place of the CD4066 & I used a static 50% duty cycle (from a PIC) to the MOSFET gate - what I scoped from the output of the opamp was just downright ugly, but this didn't surprise me, because obviously half the time there's going to be no phase shift, then the other half of the time there's going to be the maximum phase shift for that stage (i.e. the max phase shift that the cap/resistor combo will allow for that stage)....far from averaging, you get the output switching between no phase shift & full phase shift which looks bad on a scope. Is this one of the situation where it doesn't atter what it looks like on a scope, becuase the avergae phase shift is 50% ...it sounds ok, or have I missed something findamental here?

[merlinb]

Funny this should come up- I am currently venturing into a PWM phaser design myself!

The clock signal applied to the switching element is a pulse waveform whose duty cycle varies slowly from a high value to a low value and back again. Usually it won't go all the way from 0-100%, more like 10-90%. The frequency needs to be at least twice the highest audio frequency of interest, preferably much more. This might typically be 50kHz.

For my own experiments I started by building two 4-stage phase circuits that were identical except that one used JFETs, the other 4066 CMOS switches. I then drove both with the same 30kHz clock and audio signals, and examined the outputs to see which was better. (See below)

I found that the CMOS version suffered much less control voltage feedthrough, and also acheived more phase shift with the 10-90% PWM I had available (about 380 degrees with 4 stages). Changing the clock frequency didn't imporve the noise noticably. With this in mind, I'm going to stick with the 4066 as I develop the circuit.

One thing that is VERY important is to keep the PWM-generation circuit separate from any audio ICs, and use good PSU decoupling/regulation to keep the hash out of the audio circuit.

The next step for me is to design a low-cost PWM modulator.

FET circuit. Upper trace is the audio input, lower trace is the phase shifted output at the worst PWM setting.


CMOS circuit. Upper trace is the audio input, lower trace is the phase shifted output at the worst PWM setting.

[Gurner]

Thanks maybe it's my particular circuit...but the output (test) sine wave is just swamped in switching clock to the point where you can barely see it! (I'll try & capture some scope traces).

It'd be nice if you could apply a 50% static duty cycle clock...just to see what you're getting!

I was using a 15.625khz clock (on the basis that most old b@stards can't hear that...so any clock bleed won't be heard) ...the PWM clock is a piece of p1ss to implement in a PIC...but for now I just wanted to see what was happening to the phase at differing (static) duty cycles....and it ain't nice!

[nelson]

Funny this should come up- I am currently venturing into a PWM phaser design myself!

The clock signal applied to the switching element is a pulse waveform whose duty cycle varies slowly from a high value to a low value and back again. Usually it won't go all the way from 0-100%, more like 10-90%. The frequency needs to be at least twice the highest audio frequency of interest, preferably much more. This might typically be 50kHz.

For my own experiments I started by building two 4-stage phase circuits that were identical except that one used JFETs, the other 4066 CMOS switches. I then drove both with the same 30kHz clock and audio signals, and examined the outputs to see which was better. (See below)

I found that the CMOS version suffered much less control voltage feedthrough, and also acheived more phase shift with the 10-90% PWM I had available (about 380 degrees with 4 stages). Changing the clock frequency didn't imporve the noise noticably. With this in mind, I'm going to stick with the 4066 as I develop the circuit.

One thing that is VERY important is to keep the PWM-generation circuit separate from any audio ICs, and use good PSU decoupling/regulation to keep the hash out of the audio circuit.

The next step for me is to design a low-cost PWM modulator.

FET circuit. Upper trace is the audio input, lower trace is the phase shifted output at the worst PWM setting.


CMOS circuit. Upper trace is the audio input, lower trace is the phase shifted output at the worst PWM setting.

I was thinking of using a CD4046 to double the frequency on the output of the electric druid TAPLFO to clock some 4066.  

[merlinb]

It'd be nice if you could apply a 50% static duty cycle clock...just to see what you're getting!

I was using a 15.625khz clock (on the basis that most old b@stards can't hear that...so any clock bleed won't be heard) ...the PWM clock is a piece of p1ss to implement in a PIC...but for now I just wanted to see what was happening to the phase at differing (static) duty cycles....and it ain't nice!

At 50% duty cycle I got slightly less noise, and a different amount of phase shift of course, but it didn't look much different.

Your clock frequency needs to be much higher- remeber about intermodulation; it's not just the clock frequency that needs to be inaudible, but also the sidebands!

[Gurner]

I chose 15.625khz, because at a PIC MCU clock of 16Mhz, that  allows 1024 duty cycle steps & 15.625khz is about 3 x the 3rd harmonic of the highest guitar fundamental - this is just for a test circuit (to help me square away in my head what's going on)& not an actual phaser.

So what's actually happening here?

Is the jfet (or CD4066) acting as a crude voltage controlled variable resistor (for example perhaps the high clock frequency is being somewhat filtered by the jfet capacitance?)...because if it's acting as a switch, then I'm struggling with the idea of an 'average' phase shift. For example, I got my circuit to toggle between full phase shift & no phase shift (by  toggling 0V & VCC to the mosfet gate ...essentially 0% duty & 100% duty)...the sine wave output from the opamp was totally clean...but the phase obviously jumpingin sympathy with the gate signal...so it was jumping between zero phase shift & about 40% phase shift (40% just happens to be the max amount of phase shift wat the test frequency I'm using through one stage)...so that was a nice slow toggle....if I then increase the toggle speed, it jumps between the two extremes faster - in essence that's a 50% duty cycle, but at no time did I see a nice phase shifted signal ..just a mish mash of the signal moving between 0% phase shift & 40% phase shift.

Whassgoinon?

[merlinb]

Is the jfet (or CD4066) acting as a variable resistor

Yes. At 0% PWM it has maximum resistance, at 100% PWM it has minimum resistance, and at 50% it has half the maximum resistance. And so on!

By slowly varying the PWM the resistance slowly changes, and with it the phase shift; just like a regular phaser.

You don't want to instantly chop between 0% and 100% PWM, you want to slowly blend from one extreme to the other, through all the intermediate PWM values.

[Gurner]

Is the jfet (or CD4066) acting as a variable resistor

Yes. At 0% PWM it has maximum resistance, at 100% PWM it has minimum resistance, and at 50% it has half the maximum resistance. And so on!

By slowly varying the PWM the resistance slowly changes, and with it the phase shift; just like a regular phaser.

You don't want to instantly chop between 0% and 100% PWM, you want to slowly blend from one extreme to the other, through all the intermediate PWM values.

ok cool, but clearly a varying duty cycle waveform is not a varying voltage unless it's smoothed/averaged - so bearing in mind it's a varying duty cycle square wave we are applying, where's the smoothing happening? (at least this info accounts for why my MOSFET give awful results - it's either on of of...no shades of 'variable resistance' grey in between!) ...why don't these PWM phasers have an LPF prior to the gate controlling each stage?

[nelson]

On or off are the two variable states in a SPST switch. It's the time difference between on and off that controls current flow over time.

If a switch is on 100% of the time, 100% of current flows. If a switch is on 50% of the time, only 50% of the possible current flows in a given time frame.

[Gurner]

On or off are the two variable states in a SPST switch. It's the time difference between on and off that controls current flow over time.

If a switch is on 100% of the time, 100% of current flows. If a switch is on 50% of the time, only 50% of the possible current flows in a given time frame.

I understand all that ....but not fully understanding the impact of that outcome - like I say with the switch open (0% duty cycle)....no phase shift  ....but with the switch closed =max phase shift. I'm not grasping how 50% duty cycle yields a 'somewhere in between' smooth shift ...what you should end up with say a 50% duty cycle, with zero phase shift 50% of the time & max phase shift for the other 50% of the time....but a 50% duty cycle that doesn't equal 50% of the max phase shift...it means it's jumping between both phase shift extremes a lot! So where is the smoothing happening?

[slacker]

The switch is supposed to act like a variable resistor. 100% duty cycle its a tiny resistance, 0% it's open or some massive resistance. Between the two extremes the aparent resistance varies with duty cycle. In other words the rate at which the C1 caps charge and discharge varies with duty cycle. The phase shift then varies in the same way as any other phaser. Thats the theory anyway.

[merlinb]

The switching happens so fast compared with the audio that during a single switch period, the audio voltage applied to the switch appears constant.

The AVERAGE current through the switch is the current that flows when the switch is ON, divided by the switch period (or multiplied by the switching frequency- same thing). As you make the ON period shorter, the AVERAGE current gets less.

Resistance is voltage divided by current. The applied voltage we assumed was constant, so the AVERAGE resistance of the swtich appears higher (as far as the audio is concerned) as you make the ON time shorter. And vice versa..

[Gurner]

The switch is supposed to act like a variable resistor. 100% duty cycle its a tiny resistance, 0% it's open or some massive resistance. Between the two extremes the aparent resistance varies with duty cycle. In other words the rate at which the C1 caps charge and discharge varies with duty cycle. The phase shift then varies in the same way as any other phaser. Thats the theory anyway.

So I guess the answer here, is that it's C1 that's doing the 'smoothing' (in  combination with it preceding resitance.)


This was my test setup, but the scoped output looks terrible...



...is there a flaw in the approach? (ie mosfet vs jfet ....plus the way I've arranged it?)

[merlinb]

...is there a flaw in the approach? (ie mosfet vs jfet ....plus the way I've arranged it?)

In that configuration the drain voltage will swing postivie and negative with the audio signal, so the body diode of the FET may conduct, creating all sorts of havoc.
A JFET would need the clock signal to swing negative during the OFF period, creating more complication.

It would probably be worth your while to use CMOS switches and configure the circuit like the one in your first post (that's what I did).

[GFR]

For example, consider this one....

This fragment comes from a project in Elektor magazine. I think you can find the complete schematics and even the article in the web. It was a big project IIRC 16 stages, plus a complicated sawtooth oscillator that was compared to the LFO to generate the PWM control signal.

There's another approach to switched phasers, using a switched capacitor notch filter where the notch is controlled by the switching frequency and not by duty cycle. There was a magazine project by RA Penfold that used a MF10 chip (a switched capacitor filter in a chip).

I've got this stuff in paper _somewhere_... If I can find it I can give you some more info on those projects.

VOLUME 19 No. 4 APRIL 1983

SWITCHED CAPACITOR PHASER by R. Penfold .. .. .. 40
Phaser sound effects based upon the twin filter MF10 CN chip

Elektor PWM
http://www.uni-bonn.de/~uzs159/phaser.html
(I've got the article, but it's from the Brazilian edition, if you can read portuguese... )

[Gurner]

(I've got the article, but it's from the Brazilian edition, if you can read portuguese... )

falo portugese! (minha esposa e brasileira!) ...mas eu estou brincando...nao quero, por que....

I hope to use a PIC as the PWM source so a switched capactor would be no good. ..PICS are great at switching duty cycle, but not so great at switchiing frequency.

[GFR]

Sorry, I think I was not clear.

The article that I have in Portuguese is the PWM phaser from Elektor magazine, I can scan it.

The Penfold phaser (switched capacitor) is in English, altough I think I'd have a hard time to find my copy

[ElectricDruid]

I've been thinking about PWM phasers too. Like Gurner, using a PIC to replace all that complicated PWM LFO stuff just looks too good to miss.
How did you get on running the 4066 from the PICs +5V output? Did you have the 4066 on +5V to, or is that at +9V? Does it interface ok?

The switching frequency has to be sufficiently high that you can average the results out and still expect to see your audio signal. Practically, "averaging" here is done by a lowpass filter, so I need a lowpass filter on the output that will pass my highest audio frequency and still give me good rejection of any clocking noise. If the output filtering is (say) 12dB/oct, I might want three or four octaves between my lowpass filter cutoff frequency and the clock frequency. So for example 15KHz top end for audio would give us 60KHz+ clock (2 octaves). That still only gives us -24dB clock rejection, ish.  Hence the need to get the clock higher.
The important part is that it's an average. The phase shift only really has two settings (switch on and switch off!), but for "low" frequencies (relative to the clock) the average result will be a phase shift dependant on the duty cycle. That average has to be over some period of time which is small enough to not interfere with the audio.

Tom

[Gurner]

Sorry, I think I was not clear.

The article that I have in Portuguese is the PWM phaser from Elektor magazine, I can scan it.

The Penfold phaser (switched capacitor) is in English, altough I think I'd have a hard time to find my copy

Whilst I can speak basic-intermediate Portuguese, I doubt I'd get on too well with techie Portuguese - but thanks anyway :-)

[GFR]

So for example 15KHz top end for audio would give us 60KHz+ clock (2 octaves). That still only gives us -24dB clock rejection, ish.

It's worse That's 24dB down at 60kHz, but you will have 15kHz sidebands, the attenuation will be even less at the beginning of the sidebands @ 60-15=45kHz.

OTOH, you naturally have less energy at the high end of the 15kHz band, and even if it's poorly attenuated or not filtered at all you can't hear it anyway. It will only disturb you if it interferes with other similar high frequency stuff (sound card or digital fx sample rate, tape recorder bias) or distorts something plugged after it, and generates intermodulation in the audible range.

With a discrete PWM LFO you can have a much higher frequency and make filtering easier. It doesn't need to be as complicated as the elektor design - you need a sawtooth or triangular (easy) and a comparator. The very difficult part is the comparator, you want it to be really fast and with a clean "digital" output.

BTW not an issue with a phaser but if you use the PWM'ed signal in the feedback loop of an opamp (like I did in the compressor in another thread) you can't have a 12dB filter, because you already have the compensation of the operational, if you put 2 additional poles inside the feedback loop that's 3 poles and it WILL oscilate.