Question about BBD clocking

[Govmnt_Lacky]

Correct me if I am wrong but...

When I want to substitute a BBD with one that has a higher delay in a circuit, don't I need to increase the clock frequency at a multiple of the increase of the delay?

Example:

I want to build a circuit that calls for the use of a 256 stage BBD however, I plan to use a 512 stage delay in it's place. Shouldn't it work if I double the required clock frequency?

This is what was done in the A/DA flanger clone when the SAD1024 (used in parallel making it a 512 stage delay) was substituted with the MN3007 (1024 stage). The clock frequency was doubled as the delay stages were doubled.

Thoughts??

[Mark Hammer]

In general, you are correct.  The exception is the substitution of an SAD1024 for either an MN3007, MN3004 or MN3010.  The SAD1024 has two sections of 512 stages each, like the MN3010.  If configured as two parallel 512-stage sections, like an MN3010, OR configured as two series 512-stage sections, like an MN3010 configurd the same way, then no change in clock frequency is required to achieve the same delay time.

If half of an SAD1024 is used to replace a 512-stag eMN3004, then no change in clock frequency is required.

If an SAD1024 is used as a 1024-stage (512+512) replacement for an MN3007, then no change in clock frequency is required.

Make sense?

[Govmnt_Lacky]

Thanks Mark!!

The examples I used were general. My plan is to substitute an R5106 (256 stage) with an R5107 (512 stage)

[Mark Hammer]

Subbing a higher-capacity BBD, run at a higher clock frequency, to replace a lower-capacity one run at a lower frequency, can often work out better than the reverse.  The reason is that all filtering in the circuit is predicated on tackling a particular range of clock noise and aliasing.  And if you're above that clock range, then you know the filtering will be sufficient.  Move in the other direction, towards a lower clock frequency, and there is no guarantee that the on-board LP filtering will do the job.

Obviously there is still the matter of whether the existing circuitry will easily support higher clock frequency (e.g., if it uses an MN310x clock chip), but whatever a 5106 is attempting to do will likely be easily tackled by a 5107.

[Govmnt_Lacky]

Your knowledge is POWER Mark!  

I suspected as much but, wanted to consult with the knowledge base.

I am attempting to design my own PCB for the DEM V4/5. Got most of the Rev Engineering done. Just need to get off my arse and put it into Express PCB  

That reminds me...

Anyone got a good, compact layout for a DEM Version 4 or 5? 

[Mark Hammer]

Well, it is an opinion that comes from some thought, but do not consider it the last word.  I'm just a humble psychologist with an interest in such things.  Others here have far more knowledge about the EE side of it, so consult them too.