Understanding BBD Clock Drivers

[YouAre]

I have a few analog delays and flangers ready to be built, but I wanted to understand the different drivers before tackling them.

It's my understanding that some delays like the Way Huge aquapuss uses an mn3101 clock driver, similar to the Boss CE-2 Chorus. Is there anything special behind this clock driver chip, or is it simply a convenient package that puts out a clean variable frequency waveform?

Looking at effects like the ADA Flanger, the EHX Deluxe Memory Man, EHX Small Clone, they all use a cd4047 multistable vibrator which is "wiggled" by another LFO for modulation. Why is the cd4047 used specifically over any other oscillator? I want to say that the multistable vibrator puts out a clean high frequency that's able to drive a BBD. Can anyone confirm this for me?

Also, what are the current limitations of these chips? Say if I wanted to drive 2-4 BBD's, would I necessarily need multiple clock drivers? Or could I use a single driver and amplify the current? Alternatively, is it possible to control 2 clock driver circuits simultaneously? If so, can we expect a reasonably uniform response from the two drivers?


When it comes to flangers, I see that The Electric Mistress, MXR 117, and the ADA Flanger all use a cd4049 hex inverter between the clock driver circuits and the BBD. What does this do to the signal exactly?


Finally, what is the relationship between clock frequency and delay time? Is it something that is easily inversely proportional? Or are there wide tolerance factors in play?



I know it's a lot of questions, but I've searched and read a lot to further my understanding and these are questions I still have. Thanks for the help guys!

[armdnrdy]

Your correct about the MNXXXX series clock generator/driver ICs. They are pretty much a convenient package. They supply the clock and the appropriate VGG voltage for the MNXXXX series BBDs. The data sheet states that they will drive up to two 4096 stage BBDs. These clocks have a limited frequency range. 

The CD4049 hex inverter is used as a buffer allowing the clock to be run at a higher rate.

Clock frequency and delay time will depend on how many stages the BBD has. You can clock different stage delay ICs at say 10Khz but will produce different delay times due to the amount of stages that the signal has to pass through before exiting the BBD. The lower the frequency the longer the delay.

Study BBD data sheets that are available on the net. Also, Look up some of the things I've touched upon in the search function on this forum. There is a wealth of information.

[R O Tiree]

1.  Some of the BBD chips require a reference voltage (Vgg) of 14/15 of Vdd.  The Clock driver chips were designed to go hand in hand with their respective BBDs and one of the pins on the clock driver supplies that reference voltage without the need for any more external circuitry.

2.  There are other ways of getting that reference voltage aside from relying on a specific clock driver chip to do it for you.  I suspect that cost had something to do with EHX and others deciding to use a cheaper oscillator and then some kind of voltage divider to provide the reference.

3.  I've used one driver for 2 BBDs before with no problems.

4.  BBDs chips require 2 clock signals, one being the inverse of the other, ie they will never be both high or both low at the same time.  Have a look at the datasheet for, say, the MN3208.  There's a simplified diagram of the stages and how they work.  Each stage consists of 2 FETs and a capacitor on the diagram shown.  It is the caps that store each voltage sample and the FETs act as doors.  Applying those clock pulses to the gates of those FETs, switching the FETs on and off in turn, allows you to shut one door and open the next, so allowing the voltage samples to flow from one cap to the next in sequence.  An MN3XXX clock driver chip supplies both the clock signals required.  If you use a CD4047, then you'll need to feed its output signal direct to one of the clock pins on the BBD and via an inverter (CD4049) to the other clock pin.  I don't think that this has anything to do with the speed you can drive it - it's just a requirement for the BBD that it gets 2 opposing clock pulse trains.

5.  Again, have a look at the datasheets.  Taking the MN3208 as an example, the delay times are given as 10.24ms to 102.4ms.  Further down it denotes acceptable clock frequencies ranging from 10kHz to 100kHz.  That tells you the relationship, then.  The faster the clock frequency, the shorter the total delay time through the chip (because you're opening and shutting the doors faster and getting more samples through each stage per second).  OK, time for a bit more thought about this... You might think that 2000 stages (roughly) divided by 10kHz might give you 0.2s delay (200ms), but it doesn't... it only gives you 100ms.  Why?  Have a closer look at that diagram again.  Clock pulse 1 (CP1) drives stages 1, 3, 5, 7, etc and CP2 drives stages 2, 4, 6, 8, etc.  Just as in real life, where a bucket brigade requires people with 2 hands to deliver the buckets along the line to the fire, so it need actually 4 FETs and 2 caps to accomplish the same trick electronically.  Think about it... if all the gates went high at the same time, then all the voltages in all the caps would just average out and that would be that.  Instead, one door opens and the 2 either side of it shut... charge gets passed along.  In the real-life bucket brigade, you take a bucket with your left hand (odd numbered stage), it swings down and (clocks flip over) you transfer it to your right (even numbered stage) and swing it up towards the next person's left hand and (clocks flip the other way again) pass it on.  Neat, isn't it?

[Mark Hammer]

If you look at the data sheets for the Panasonic/Matsush*ta BBD chips, one of the specs you will see in capacitance on the clock input pins.  An MN3007 shws 700pf capacitance.  An MN3005 shows 2800pf capacitance (4 x 700, right?).

That input capacitance acts like a low-pass filter, albeit with a very high corner frequency.  When the clock frequency is low enough (i.e., within the range specified by the MN3101/3102 datasheet), that capacitance has no impact.  When the clock freuqnecy goes higher than a certain range, that input capacitance starts to behave like a lousy cable between your guitar and amp.  Instead of losing treble, though, what happens is that the nice crisp square wave from the clock generator starts to become more trapezoidal, and eventually triangular, as the input capacitance adds lag to the rise and fall times of the clock pulse.

Why does that matter?  It matters because when they work properly, BBDs seamlessly hand off analog samples from one storage cell to another, with no perceptible gaps in between.  When the clock pulse that tells the FETs in the storage cells to fork over their stored voltage to the next cell takes a little while to reach the critical voltage that enables the switching action inside the BBD, you end up with gaps between successive samples.  If we can use the "bucket brigade" analogy, it's as if the person handing you the bucket is struggling to lift it, and once you get the bucket, YOU struggle to hand it off to the next guy, and so on.

When it comes to guitar cables and treble loss, we find that having a buffer between the guitar and the amp overcomes the cable's capacitance.  Similarly, if one wishes to go beyond the stipulated clock range shown in the MN3xxx datasheets, you need to be able to deliver more current to the BBD clock input pins, so as to overcome the effects of that capacitance.  You can't change the clock pin input capacitance, but you can compensate for it.

The MN3101/3102 are limited in how much current they can deliver.  The choice to use CMOS chips instead is based on their ability to deliver more current to the BBD clock pins.

As an aside, the Reticon SAD-1024 was a frequently preferred choice for flangers, largely because its input capacitance on the clock pins was much lower (110pf) than on the MN3007, allowing it to be clocked - unaided - at much higher frequencies.

[~arph]

Good reads guys!

[R O Tiree]

Ahh.  Thanks, Mark.  I hadn't thought through that far.  The clues were there all along in the trapezoidal clocking waveforms on the datasheet and I didn't twig.  It begs the question why Matsush!ta didn't do that in the first place?  Gut reaction tells me that one door has to close before the next one opens (to continue with my analogy above) and a pair of exactly square waves would not achieve that if they have a 50:50 duty cycle, so a certain amount of capacitance to skew the waves off dead-square was just what they needed for the band of delay times they designed for?  Is the input capacitance on the SAD1024 right in the "Goldilocks" spot, making it just as capable in a flanger as it is in a long-period delay?  Could/should Matsush!ta have tightened things up a bit in that regard?

Bit by bit, the reasons behind design choices made many years ago become clearer and the jigsaw more complete.

[Mark Hammer]

Well, keep in mind that the need for high clock frequencies is rather specific to flangers.  After all, that is the only real application where the shortest possible audio delay has some practical use.  When it comes to chorus and delay, the clock range offered by both the 3101/3102 and the MN30xx/32xx BBDs is more than adequate, and the real push is for slower clock frequencies (to squeeze more delay time out of the BBD), rather than faster.  And keep in mind what the single biggest end-use of BBDs was for many years: voice-mic echo on karaoke machines.

Take all that into account, and the MN3101 offers a very compelling package to conveniently take care of 99.5% of applications.

[StephenGiles]

Why was the 4047 used for clock driver? Answer - because it was cheap and did the job, it's as simple as that

[R O Tiree]

Ah, yes... echo... that wonderful invention that allows drunken bums in bars who couldn't hold a note steady if their lives depended on it believe that they can actually do so.