Two phase clock generator

Started by armdnrdy, October 22, 2012, 01:26:55 PM

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armdnrdy

I was wondering if anyone is familiar with either of these circuits and if they are good to go.

http://www.aronnelson.com/gallery/main.php/v/diyuser/Clock+generators.jpg.html

I lifted them out of an Archer SAD1024 data sheet. I'm finishing up the BBD tester design in which I had originally planned to use the MNXXXX series clock generator. I chose that clock for its simplicity, but unfortunately it has a limitation in this design.

I've looked over the 4013 clock in the MXR M-117 but it seems to be of a different design than the generator in the data sheet.



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R O Tiree

The top one (made from the quad-NOR 4001 chip) should give you frequencies from 5kHz up to about 400kHz.  Roughly...
...you fritter and waste the hours in an off-hand way...

oldschoolanalog

As you are really only interested in max delay (clock=~10kHz) this should work okay. Personally I would add a 4049 buffer to insure a strong clock signal. Probably helpful for the longer stage BBD's but may not be necessary for the low clock f's you will be using.
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Fender3D

M-117 is roughly 3 inverters + a flip-flop...
I would use a 4047, check ADA Flanger, small clone or clone theory...
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armdnrdy

Hey guys, thanks for the replies,

The issue that I'm trying to solve is the clock signal voltage from either clock line from a two phase clock is too low to drive the counter ICs. The voltage seems to be around half VDD of the supply. Half VDD voltage is too low for CMOS logic. I assumed that this was inherent in the design of the MNXXX clock until I bread boarded the 4013 clock that I posted and ended up with the same issue. I now understand that this is inherent in two phase clock designs.

In an earlier post, I asked about increasing the amplitude of a clock signal. I looked all over the net and came up with a few options, none of which worked properly. Some designs did absolutely nothing, and some distorted the square wave too much.

Today I was looking into another option. Since the clock voltage I'm starting out with (4.5 volts) falls within the TTL logic range, and I need to increase that to the CMOS range, (7 volts +) I believe that I can use a TTL to CMOS converter IC. (Low to high voltage translator) There are a variety of ICs available to achieve this logic conversion with minimal degradation of the signal.

CD4504BE
CD40109B
HEF4104B
MC1450B

I wish I had to decrease the voltage instead of increasing it. It would be much easier!

If anyone can come up with an easier way to do this, PLEASE share your thoughts.
I just designed a new fuzz circuit! It almost sounds a little different than the last fifty fuzz circuits I designed! ;)

R O Tiree

I'm sure you can run the 4000 series from just 5V, can't you?  I think the minimum is 3V pretty much across the range and the max varies from 15-18 or so, depending on which chip it is.
...you fritter and waste the hours in an off-hand way...

Fender3D

Usually you'll have a voltage from almost 0 to almost Vcc from CMOS oscillators...
check it with a o'scope.
If you measure it with tester you'll have ~1/2Vcc 'cause duty cicle is 50/50...
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armdnrdy

Quote from: Fender3D on October 23, 2012, 03:13:55 PM
Usually you'll have a voltage from almost 0 to almost Vcc from CMOS oscillators...
check it with a o'scope.
If you measure it with tester you'll have ~1/2Vcc 'cause duty cicle is 50/50...


I might be wrong about this but I understand a 50% duty cycle as being equal high and low periods. If I take a measurement with a DMM between one clock line and ground, shouldn't I be reading the peak/high voltage?
I just designed a new fuzz circuit! It almost sounds a little different than the last fifty fuzz circuits I designed! ;)

armdnrdy

Quote from: R O Tiree on October 23, 2012, 03:04:16 PM
I'm sure you can run the 4000 series from just 5V, can't you?  I think the minimum is 3V pretty much across the range and the max varies from 15-18 or so, depending on which chip it is.

Hey Mike,

I've thought about your suggestion. I already have the board design routed, and unfortunately the power section and the clock section are in two opposite corners of the board. I would have to add a 5 volt voltage regulator for the bulk of the design and power the clock and BBD with 9 volts. I would have to redesign the sine wave oscillator as well.

This is killing me! I just need to increase the voltage of one of the clock lines 3 more volts!
I just designed a new fuzz circuit! It almost sounds a little different than the last fifty fuzz circuits I designed! ;)

slacker

Quote from: armdnrdy

I might be wrong about this but I understand a 50% duty cycle as being equal high and low periods. If I take a measurement with a DMM between one clock line and ground, shouldn't I be reading the peak/high voltage?

If the signal is slow enough, probably below audio your meter will read the full supply voltage for half the cycle and 0 volts for the other half. At the speeds you're running at your meter will average that out and show about half the supply. Both of the circuits you posted will swing between 0 volts and the full supply. I can't see why they wouldn't drive your counters.
If you do need to level shift them you can use an npn transistor. Connect the emitter to ground, the collector to the input of the counter with a 10k resistor from there to the counter's supply voltage. Then connect the output of your clock through a 10k resistor to the base of the transistor. That should work.

armdnrdy

Okay, that's what I get for trusting my eyes and my $400 Fluke V DMM!

I usually take voltage measurements with my DMM because it's quicker and easier. When I scoped the output of the clock, I read 9 volts at the peak/high of the square wave. So, the only limitation I had was my DMM!

I also bread boarded a few different clocks to check the difference.

4013...not so good at 10kHz. The voltage varied between the clock lines and the square wave showed distortion at the beginning of the high cycle. The duty wasn't that good either.

4047...No problem at 10kHz. Good clean square wave, good voltage between the two clock lines, and duty cycle 51%
I think that one is a keeper. (Thanks Fender3D for the suggestion)

There's also something else about the 4047 that I might find useful in this design. If my calculations are correct, to achieve the BBD stage number at the LED display, I need to send the counter ICs a 20kHz signal. I was planning to do that with a 4011 frequency doubler circuit tapped into one of the clock lines, but the 4047 has a buffered oscillator output pin with double the frequency and a duty cycle of 52.5. I believe I can use this output to drive the counter ICs. I tested this output by driving a LED directly and checking voltage, wave form, and frequency at the clock outputs. I didn't find any problems while using this pin.

Any thoughts?
I just designed a new fuzz circuit! It almost sounds a little different than the last fifty fuzz circuits I designed! ;)